Description

Drive SOC verification from feature extraction through tape-out and productization.

Responsibilities

• Develop test plans for patterns at the SOC level.
• Create, verify, and deliver patterns to the Product Engineering team for silicon validation.
• Manage the full verification lifecycle from initial feature extraction to productization.

Required Skills

• 5+ years of experience in SOC Verification.
• Proficiency with Verilog.
• Hands-on experience with UVM.
• Strong knowledge of SystemVerilog (SV).
• Experience with scripting languages.
• Ability to develop and verify patterns for silicon validation.

Preferred Skills

• Any Graduate degree.

Key Skills

Education

Any Graduate