Description

Experience: 6-12 Years

Position Overview:
Verification Engineer with hands-on experience in SystemVerilog and UVM-based environments. Strongly skilled in testbench architecture and development, debugging, and test execution across complex SoC/ASIC projects.
Key Responsibilities:
* Develop and enhance UVM-based testbenches and verification components
* Translate architecture specifications into detailed verification test plans
* Create and execute functional coverage models, work toward coverage closure
* Perform simulation regression runs, manage results, and debug test failures
* Identify RTL issues, verify fixes, and provide root-cause analysis
* Implement checkers and assertions to validate design functionality
* Contribute to gate-level and low-power simulation verification
* Coordinate with design and architecture teams to resolve issues
* Exhibit strong communication skills and flexibility to meet project timelines
Requirements:
* Proficiency in SystemVerilog, UVM, and testbench methodologies
* Experience in debugging complex functional failures
* Exposure to formal verification techniques is a plus
* Ability to work independently and collaboratively in a fast-paced environment
* Willingness to extend work hours when required to meet critical project milestones

Key Skills

Education

Any Graduate