Description

You will own SoC system verification and IP integration testing within a UNIX environment. You will develop testbenches, debug embedded software, and implement RTL in FPGA environments.

Responsibilities

• Develop and maintain SoC verification testbenches using SystemVerilog, including SVAs, cover-properties, and coverage groups.
• Program and debug C test cases to verify IP integration, translating RTL subsystem environments for FPGA verification.
• Debug sophisticated designs using practical embedded software knowledge and implement ASIC/SoC RTL in FPGA environments.
• Manage version control with SVN/Git and track tasks using Jira.

Required Skills

• 7+ years of experience in RTL Verification utilizing SystemVerilog and SVA.
• Proficiency in C programming and object-oriented coding with C++.
• Experience with simulation tools including Verdi/VCS, QuestaSim, and Cadence tools.
• Strong UNIX/Linux command line skills and shell scripting using Python, Tcl, Makefile, or Bash.
• Working knowledge of AMBA bus standards.
• Experience handling data formats including YAML and JSON.
• Hands-on expertise in debugging complex designs.

Preferred Skills

• Experience with SV UVM testbenches and UVM Verification IPs (VIP).
• Knowledge of Xilinx FPGA technology and Synopsys tool flows.

Key Skills

Education

Any Graduate