Description

You will own DFT architecture, implementation, and verification tasks. You execute scan, ATPG, simulation, and GLS workflows. You perform MBIST insertion and simulation while debugging issues. You manage technical documentation including uArchitecture and SoC Integration Specifications. You use scripting to automate design and verification workflows.

Responsibilities

• Execute DFT architecture tasks including Scan, ATPG, simulation, and GLS.
• Perform MBIST insertion and simulation.
• Debug simulation issues and manage technical documentation such as uArchitecture and SoC Integration Specifications.
• Utilize scripting languages to automate design and verification workflows.

Required Skills

• 6+ years of experience in DFT design and implementation.
• Hands-on experience with Synopsys, Cadence, or Mentor tools including Tetramax, Modus, Tessent, and DC tools.
• Proficiency in Scan, ATPG, Simulation, and GLS.
• Experience with MBIST insertion and simulation.
• Scripting proficiency in Python, Perl, TCL, or Shell.
• Strong simulation debugging skills.
• Ability to write uArchitecture and SoC Integration Specifications.

Preferred Skills

• Knowledge of JTAG.

Key Skills

Education

Any Graduate