Description

You will own DFT architecture, implementation, and verification tasks, including scan, ATPG, simulation, and GLS workflows.

This role is on-site.

Responsibilities

• Execute DFT architecture tasks including Scan, ATPG, simulation, and GLS.
• Perform MBIST insertion and simulation while debugging issues.
• Manage technical documentation such as uArchitecture and SoC Integration Specifications.
• Utilize scripting languages to automate design and verification workflows.

Required Skills

• 6+ years of experience in DFT design and implementation.
• Hands-on experience with Synopsys, Cadence, or Mentor tools (Tetramax, Modus, Tessent, DC).
• Proficiency in Scan, ATPG, Simulation, and GLS.
• Experience with MBIST insertion and simulation.
• Scripting proficiency in Python, Perl, TCL, or Shell.
• Strong simulation debugging skills.
• Ability to write uArchitecture and SoC Integration Specifications.

Preferred Skills

• Knowledge of JTAG.

Key Skills

Education

Any Graduate