Description

You will lead detailed block design and RTL implementation from system requirements and evolving specifications.

This role is remote.

Responsibilities

• Develop hardware architecture from specification documents and design top-level RTL, including integration of blocks, clocks, resets, and configuration registers.
• Write RTL code for IP development and integration using Verilog, SystemVerilog, or VHDL.
• Execute low power design using UPF or CPF and collaborate with Synthesis, STA, PD, DFT, and verification teams to meet functional, performance, power, and area goals.
• Perform static checks including Lint, CDC (Spyglass), synthesis, LEC, and STA.
• Debug and fix functional breaks and timing constraints.

Required Skills

• 12+ years of experience in Logic (RTL) Design.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Experience with Lint/CDC (Spyglass), synthesis, LEC, and STA.
• Knowledge of JESD204C block design and related verification experience.
• Experience with low power implementation using UPF/CPF.
• Scripting proficiency in Perl, Python, or TCL.
• Ability to design top-level RTL, including clocks, resets, and configuration registers.

Preferred Skills

• Experience with advanced peripheral bus IPs such as GPIO, UART, SPI, SW, JTAG, and I2C.
• Knowledge of low-speed bus protocols (AMBA/OCP) and high-speed serial protocols (PCIe, USB, or Ethernet).

Key Skills

Education

Any Gradute