Description

You will own the static timing analysis and timing closure for ASIC designs.

Responsibilities

• Perform Static Timing Analysis (STA) to ensure timing closure of ASIC designs.
• Identify and resolve timing violations through collaboration with design and verification teams.
• Develop and maintain timing constraints and scripts for STA processes.
• Collaborate with cross-functional teams to optimize design performance and meet timing requirements.
• Document timing analysis results and provide reports to the design team.

Required Skills

• 4 to 12 years of experience in Static Timing Analysis (STA).
• Proficiency with Synopsys PrimeTime.
• Proficiency with Cadence Tempus.
• Strong scripting skills in Tcl and Perl.
• Experience with Verilog.
• Experience with VHDL.
• Ability to perform timing closure on ASIC designs.

Preferred Skills

• Any Graduate degree.

Key Skills

Education

Any Graduate