Description

Key Skills: Verilog, System Verilog, UVM, Python, Mixed Signal Verification, Analog Circuit Design, Cadence Virtuoso, Xcelium, TCL, Perl

Good to Have Skills: Bash scripting, formal verification, gate level simulations, spice simulators, object-oriented programming, AMS verification methodologies, technical mentoring and coaching experience, export licensing knowledge.

Roles & Responsibilities:

• Define and develop block level and top level verification strategies based on design requirements and architecture.
• Develop verification plans and verification environments from scratch on multiple projects with proven track record.
• Work on development of analog checkers, SystemVerilog assertions, functional coverage, and formal verification to reach verification goals.
• Specify and perform block and chip level RTL, gate, and mixed signal co-simulation regressions as necessary.
• Track progress against verification plan and work with designers and product engineers to achieve functional coverage goals.
• Work closely with evaluation engineers when silicon arrives to compare and contrast simulation results with expectations.
• Take complete ownership for complex feature verification and mentor junior verification engineers in technical aspects.
• Define and implement improvements in verification flow and methodology for enhanced efficiency and accuracy.

Experience Required: 8+ years of experience in Analog and Mixed Signal verification with expertise in constrained random functional verification, coverage, and assertions. Strong debugging, analytical and problem-solving skills required along with excellent interpersonal and communication abilities.

Education: Bachelor's or Master's degree in Electronics Engineering

Key Skills

Education

Any Graduate