Description

Own block and top-level verification strategies for analog and mixed-signal designs, ensuring functional coverage goals are met through rigorous simulation and analysis.

This role is on-site.

Responsibilities

• Develop verification plans and environments from scratch for multiple projects using constrained random functional verification.
• Create analog checkers, SystemVerilog assertions, and formal verification components to achieve coverage targets.
• Execute block and chip-level RTL, gate, and mixed-signal co-simulation regressions using Xcelium.
• Mentor junior engineers on technical aspects and define improvements to verification flow and methodology.
• Collaborate with evaluation engineers to compare silicon results with simulation expectations.

Required Skills

• 8+ years of experience in Analog and Mixed Signal verification.
• Expertise in Verilog, SystemVerilog, UVM, and Python.
• Proficiency with Cadence Virtuoso, Xcelium, TCL, and Perl.
• Strong debugging, analytical, and problem-solving skills.
• Bachelor's or Master's degree in Electronics Engineering.

Preferred Skills

• Experience with Bash scripting, formal verification, and gate-level simulations.
• Familiarity with AMS verification methodologies and technical mentoring.

Key Skills

Education

Any Graduate