Description

You will develop and maintain high-performance functional models for system-level IP, building virtual platforms to enable early firmware and OS development prior to silicon availability.

This role is on-site.

Responsibilities

• Develop, test, and maintain C++ and SystemC models for system-level IP and virtual platforms.
• Collaborate with hardware architects and RTL designers to ensure accurate behavioral modeling against specifications.
• Integrate multiple IP models into scalable system-level simulations to support software bring-up and debug system-level issues.
• Drive functional validation, debugging, and root cause analysis for hardware-software interactions.
• Optimize simulation performance and improve model efficiency for large-scale system simulations.

Required Skills

• 12+ years of experience in system-level modeling, SoC/IP modeling, or virtual platform development.
• Strong hands-on expertise in C++ for large-scale software systems and functional modeling.
• Experience with SystemC and TLM-based modeling and configuration methodologies.
• Strong understanding of computer architecture and microarchitecture concepts.
• Proven experience developing and integrating virtual platforms for firmware and software enablement.
• Hands-on experience in debugging and testing complex system-level models and simulations.
• Familiarity with Git-based development workflows and code review practices.

Preferred Skills

• Exposure to software architecture concepts for scalable and reusable model development.
• Experience contributing to architecture discussions and improving modeling methodologies.

Key Skills

Education

Any Graduate