Description

You will lead functional verification for control ASICs and IP subsystems, owning the process from verification planning to tapeout delivery.

This role is on-site.

Responsibilities

• Create verification plans based on IP design specifications.
• Build standalone IP test benches using SystemVerilog.
• Develop test cases, coverage models, and assertions to ensure functional correctness.
• Generate functional and code coverage metrics and collaborate with IP developers.
• Deliver functional test vectors required for post-silicon validation.

Required Skills

• 6+ years of hands-on experience in Logic IP Verification using SystemVerilog.
• Experience with logic verification environments including UVM.
• Hands-on experience verifying ARM Cortex-M4 based subsystems or SOCs.
• Experience with debug interfaces such as SWD and SWJ.
• Knowledge of ARM microcontroller architecture and debug infrastructure.
• Experience verifying silicon IPs such as UART, CAN-FD, I2C, SPI, QSPI, SD/UMMC, or timers/PWM.
• Strong problem-solving, written, and verbal communication skills.
• Ability to adapt to C-based and SystemVerilog-based IP verification.

Preferred Skills

• Knowledge of cryptography algorithms and data encryption/decryption verification.

Key Skills

Education

Any Graduate