Description

You will lead RTL design, microarchitecture, and debug methodology for CPU coherency IP in high-performance, energy-efficient microprocessors.

Responsibilities

• Develop SOC debug microarchitecture by collaborating with debug architects, hardware, and software teams.
• Design and implement debug mechanisms to cover functionality, performance, and power metrics.
• Execute Verilog and SystemVerilog RTL development, debug, and quality assurance.
• Work with validation and implementation teams to meet functional, performance, power, and area goals.
• Plan, track, and manage partner communications while refining methodologies to improve efficiency.

Required Skills

• 8+ years of experience developing or leading SOCs/subsystems.
• Expertise in Design for Debug (DFD) techniques including observability points, trace buffers, and error detection.
• Proficiency with ARM-specific debug solutions: CoreSight, Debug Access Ports (DAPs), Embedded Trace Macrocells (ETMs), and System Trace Macrocells (STMs).
• Strong background in digital design and RTL coding using Verilog or VHDL.
• Knowledge of ASIC/FPGA debug methodologies.
• Experience with Lint, CDC, and RDC flows and analysis.
• Familiarity with ARM Debug Interface Architecture Specification.
• Strong written, verbal, and presentation communication skills.

Preferred Skills

• Exposure to SOC architecture and design.

Key Skills

Education

Any Graduate