Description

You will build and maintain block-level and SoC models using SystemC TLM2 and C/C++.

This role is on-site.

Responsibilities

• Model SoC elements including NoC, memory controllers, cache subsystems, MMU, and TLB.
• Develop and maintain models within gem5 and QEMU frameworks.
• Implement PCIe interface modeling and manage interconnection relationships.
• Build test plans and implement check-in procedures using git or Perforce.

Required Skills

• 5+ years of experience in SoC modeling or platform architecture.
• Proficiency in C/C++ and SystemC TLM2.
• Hands-on experience with gem5 and QEMU.
• Experience modeling NoC, memory controllers, and cache subsystems.
• Familiarity with memory trace formats including Parquet and Dynamo RIO.
• Working knowledge of source control systems like git or Perforce.
• Degree in CS, CE, EE, or equivalent experience.

Preferred Skills

• Knowledge of DDR protocol validation and related firmware, BIOS, or MRC.
• Experience with PCIe or CXL protocols and x86 platform architectural elements.
• Firmware development and debugging skills in C for embedded environments.

Key Skills

Education

Any Graduate