Description

You will own the layout design, debugging, and sign-off for high-speed analog and digital blocks at TSMC 2nm and 3nm nodes.

This role is on-site.

Responsibilities

• Create custom layouts for ring oscillators, dividers, bias blocks, and pre-drivers in advanced TSMC nodes.
• Debug and resolve layout fixes across various verification flows independently.
• Execute design tasks with minimal supervision and maintain full accountability for assigned blocks.
• Ensure completed layouts meet quality standards with all verification flows clean.
• Create and verify all relevant design views using sign-off tools and produce required documentation.

Required Skills

• 5-8 years of hands-on experience in block/module layouts using Cadence Layout design tools.
• Proven expertise in TSMC 5nm or lower nodes.
• Proficiency with layout design and verification tools: Cadence Virtuoso EXL/GXL and Calibre.
• Experience with scripting languages: Shell, Perl, or SKILL.
• Bachelor's degree in Electrical Engineering or equivalent.
• Ability to work with advanced nodes (2nm/3nm TSMC NDA required).

Key Skills

Education

Bachelor's degree