Description

You will drive digital design verification through simulation and the development of complex UVM environments.

Responsibilities

• Develop UVM-based testbenches for ASICs, SoCs, or FPGAs at block, subsystem, and system levels.
• Architect and implement reusable verification components including drivers, monitors, scoreboards, and sequences.
• Create constrained-random test environments, functional coverage models, and assertions.
• Run simulations and debug complex designs using tools like Cadence Xcelium, Mentor Graphics Questa, or Synopsys VCS.
• Develop automation scripts for simulation, regression runs, and reporting using Python, Perl, or Tcl.

Required Skills

• 10+ years of experience in hardware verification.
• Expertise in UVM (Universal Verification Methodology).
• Strong proficiency in simulation and debugging.
• Experience with Assertion-Based Verification (ABV) and SystemVerilog assertions (SVA).
• Hands-on experience with simulation tools such as Cadence Xcelium, Mentor Graphics Questa, or Synopsys VCS.
• Proficiency in scripting languages including Python, Perl, or Tcl.
• Experience with version control systems like Git or SVN.
• Ability to implement code and functional coverage to drive coverage closure.

Preferred Skills

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Key Skills

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.