Description

Lead DDR memory subsystem validation across multiple SoC platforms.

You will own the validation of LPDDR4x and LPDDR5x subsystems, including memory training, performance benchmarking, and timing margin analysis. Develop, integrate, and debug firmware components such as bootloaders, memory drivers, and test hooks for RISC-V or ARM processors. Collaborate with design, firmware, and SI/PI teams to ensure correct hardware-firmware interaction and signal integrity. Execute tests and perform root cause analysis using oscilloscopes, logic analyzers, BERTs, and power analyzers. Automate validation workflows and test procedures using Python, Perl, or C/C++.

Responsibilities

• Own validation of LPDDR4x and LPDDR5x subsystems, covering memory training and timing margin analysis.
• Develop and debug firmware components, including bootloaders and memory drivers for RISC-V or ARM.
• Collaborate with design and SI/PI teams to ensure hardware-firmware interaction and signal integrity.
• Execute tests and perform root cause analysis using oscilloscopes, logic analyzers, BERTs, and power analyzers.
• Automate validation workflows and test procedures using Python, Perl, or C/C++.

Required Skills

• 15+ years of SoC validation experience.
• 5+ years of post-silicon memory subsystem validation, specifically with LPDDR4x or LPDDR5x.
• Deep knowledge of DRAM operations, memory controller architecture, and JEDEC LPDDR standards.
• Proficiency in C/C++ for low-level programming and hardware abstraction layers.
• Experience with silicon bring-up using Lauterbach debuggers, JTAG interfaces, and trace analyzers.
• Strong scripting skills in Python, Perl, or C/C++.
• Hands-on experience with oscilloscopes, logic analyzers, BERTs, and power analyzers.
• Familiarity with RISC-V or ARM architectures and embedded boot sequences.

Preferred Skills

• Experience with system-level memory performance tuning and characterization.

Key Skills

Education

Any Gradute