Description

You will own the functional, performance, and power verification closure for digital design blocks within the Graphics Core IP.

Responsibilities

• Execute verification planning, execution, and closure for assigned blocks to meet project schedules.
• Develop and execute test and coverage plans to ensure functional, performance, and power completeness.
• Create, reuse, and debug testbenches, verification components, and tests to exercise the design.
• Author detailed testplans and drive the development of test-cases, coverpoints, and assertions.
• Collaborate with architects and RTL designers to integrate new verification methodologies into existing infrastructure.

Required Skills

• 5+ years of verification experience on large ASIC development projects.
• Strong proficiency in Verilog, SystemVerilog, C, and C++.
• Experience with UVM, OVM, or equivalent methodologies.
• Hands-on experience with constrained random verification, functional coverage, and assertions.
• Solid understanding of Computer Architecture and Digital Design concepts.
• Proficiency in scripting languages including Python, Bash, Ruby, Tcl, or Perl.
• Experience using industry tools such as Synopsys VCS, VC Formal, DVE, Verdi, or GDB.
• Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.

Preferred Skills

• Experience with formal verification.

Key Skills

Education

Bachelor's or Master's degrees