Description

You will manage the complete verification cycle for complex hardware designs.

Responsibilities

• Execute the full verification cycle using strong verification concepts.
• Develop Verification IP (VIP) based on the UVM methodology.
• Implement SystemVerilog Assertions to ensure design integrity.
• Write scripts to automate simulations, regressions, and release processes.

Required Skills

• 2+ years of hands-on experience in hardware verification.
• Strong proficiency in Verilog and SystemVerilog.
• Deep knowledge of the UVM framework.
• Experience with UVM-based Verification IP development.
• Working knowledge of AMBA protocols including AXI, AHB, and APB.
• Practical experience with PCIe, Ethernet, USB, or DDR protocols.
• Ability to use scripting for automation and regression management.
• Experience implementing SystemVerilog Assertions.

Key Skills

Education

ANY GRADUATE