Description

You will define electrical verification methodologies and own the execution of system-level verification results.

This role is on-site.

Responsibilities

• Define and track detailed test plans for individual modules and top-level systems.
• Architect, design, and implement scalable test infrastructure.
• Monitor coverage metrics and manage the lifecycle of bugs.
• Support system bring-up and debugging activities.

Required Skills

• 5 to 10 years of experience in verification engineering.
• Proficiency with UVM and integration verification.
• Strong SystemVerilog and debugging skills.
• Proficiency with Python and C++.
• Bachelor’s degree in Electrical Engineering, Computer Science, or a related field.

Preferred Skills

• Master's degree in Electrical Engineering or Computer Science.
• 10+ years of experience in verification engineering.

Key Skills

Education

Bachelor's degree