Description

You will focus on the development and execution of test plans to validate FPGA designs.

Responsibilities

• Develop and execute test plans using Universal Verification Methodology (UVM).
• Validate the functionality, performance, and reliability of FPGA designs.
• Collaborate with senior engineers on digital design verification tasks.

Required Skills

• 10+ years of experience in hardware verification.
• Expertise in UVM (Universal Verification Methodology).
• Proficiency with Verilog.
• Experience with FPGA designs.
• Degree in any graduate field.

Key Skills

Education

Any Graduate