Description

You will lead verification efforts for next-generation ASIC and FPGA designs within a distributed team.

Responsibilities

• Develop test plans, implement testbenches, and create test cases to ensure functional coverage closure.
• Handle regression testing and contribute to the development of verification infrastructure.
• Debug test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve design defects.
• Review coverage metrics and modify tests or constraints to meet requirements.
• Collaborate with design, software, and architecture teams to verify the design under test.

Required Skills

• 7+ years of experience in IP-level FPGA and ASIC verification.
• Proficient in Verilog and SystemVerilog.
• Hands-on experience with UVM and developing UVM-based verification testbenches, processes, and flows.
• Proficient in scripting languages such as Perl or Python.
• Solid understanding of design flow, verification methodology, and general computational logic design.
• Experience in developing directed and random verification tests.

Preferred Skills

• Knowledge of PCIe, CXL, or other IO protocols.

Key Skills

Education

Any Graduate