Description

Key Skills: Microarchitecture, Lint, RTL Design, CDC, Static Timing Analysis, SystemVerilog, DFT, Verilog

Roles and Responsibilities:

• Collaborate with architects to define module-level specifications and develop micro-architecture documentation.
• Develop high-quality, maintainable, and synthesizable RTL code using SystemVerilog or Verilog.
• Perform Linting, Logic Equivalence Checking (LEC), and Clock Domain Crossing (CDC) analysis to ensure design quality.
• Work closely with the verification team to define test plans and debug RTL-related issues.
• Support the Physical Design (PD) team in resolving synthesis and Static Timing Analysis (STA) challenges.
• Assist in silicon bring-up activities and collaborate with failure analysis teams to debug hardware issues.

Skills Required:

• Strong experience in ASIC/VLSI design and RTL development.
• Expertise in microarchitecture design and module-level architecture definition.
• Hands-on experience with Lint, Clock Domain Crossing (CDC), and design quality checks.
• Proficiency in hardware description languages such as SystemVerilog and Verilog.
• Experience supporting Static Timing Analysis (STA) and synthesis activities.
• Knowledge of Design for Testability (DFT) concepts and implementation.
• Ability to collaborate with verification and physical design teams.
• Strong debugging and problem-solving skills for RTL and silicon-level issues.
• Understanding of ASIC design flows and hardware development lifecycle.
• Ability to work effectively in cross-functional engineering teams.

Education: Bachelor's or Master's degree in Electrical Engineering (EE) or Computer Engineering from a recognized university

Key Skills

Education

Any Graduate