Description

Define module-level microarchitecture and develop synthesizable RTL code in SystemVerilog or Verilog. Own the design quality process by performing linting, logic equivalence checking, and clock domain crossing analysis. Collaborate with verification teams to debug RTL issues and support physical design through synthesis and static timing analysis resolution. Assist in silicon bring-up and hardware failure analysis.

Responsibilities

• Define microarchitecture specifications and create detailed module-level documentation.
• Develop high-quality, maintainable, and synthesizable RTL using SystemVerilog or Verilog.
• Execute lint, CDC, and logic equivalence checks to ensure design integrity.
• Resolve synthesis and static timing analysis challenges alongside the physical design team.
• Debug RTL and silicon-level issues during bring-up and failure analysis.

Required Skills

• 7+ years of experience in ASIC/VLSI design and RTL development.
• Expertise in microarchitecture design and module-level definition.
• Proficiency in SystemVerilog and Verilog.
• Hands-on experience with Lint, CDC, and design quality checks.
• Experience supporting Static Timing Analysis (STA) and synthesis.
• Knowledge of Design for Testability (DFT) concepts.
• Bachelor's or Master's degree in Electrical or Computer Engineering.

Preferred Skills

• Experience collaborating with verification and physical design teams.
• Strong debugging and problem-solving skills for hardware development.

Key Skills

Education

Any Graduate