Description

Define microarchitecture and develop synthesizable RTL code for ASIC designs. Own the design quality process and support silicon bring-up.

This role is on-site.

Responsibilities

• Define module-level microarchitecture and create detailed specifications.
• Develop high-quality, synthesizable RTL using SystemVerilog or Verilog.
• Execute linting, clock domain crossing (CDC) analysis, and logic equivalence checks.
• Resolve synthesis and static timing analysis challenges with the physical design team.
• Debug RTL and hardware issues during silicon bring-up and failure analysis.

Required Skills

• 7+ years of experience in ASIC/VLSI design and RTL development.
• Expertise in microarchitecture design and module-level definition.
• Proficiency in SystemVerilog and Verilog.
• Hands-on experience with Lint, CDC, and design quality checks.
• Experience supporting Static Timing Analysis (STA) and synthesis.
• Knowledge of Design for Testability (DFT) concepts.
• Bachelor's or Master's degree in Electrical or Computer Engineering.

Preferred Skills

• Experience collaborating with verification and physical design teams.
• Strong debugging and problem-solving skills for hardware development.

Key Skills

Education

Any Graduate