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Xilinx India Technology Services Pvt Ltd
  Company Profile
Xilinx leads the Programmable Logic Device (PLD) market - one of the fastest growing segments of the semiconductor industry. Founded in 1984 and headquartered in San Jose, California, we are a $1.9 billion company with an employee base of over 3300 professionals across our global offices. We take pride in nurturing innovation and providing our employees with a values-driven and rewarding workplace.
 
  Job Details 
Title: 

Packaging Design Engineer

Posted On:  10/3/2020 1:23:08 AM
Designation: 

Packaging Design Engineer

No. of vacancies:  2
Qualifications:  Bachelor Degree
Essential Skills: 
Not specified
Minimum Total Experience:  2 Yrs
Job Tenure:  Contract - W2
Salary Offered:  Market Rate
Job Location:  Hyderabad Telangana India

  Job Description
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

In this key technical position, you will leverage your package design expertise and engage in the following undertakings.
Design advanced and heterogeneous integration packages to meet/exceed package and system electrical and thermal performances
Develop new package solutions including pin-out definitions, DRC/DFM and stack-up requirements
Implement chip-package design flow and LVS verification

Job requirements
Experience in CADENCE Allegro Package Designer, including constraints setup
Familiarity with AutoCAD, Gerber/ODB++/GDSII conversion software, and DFM tools
Knowledge in packaging substrate structures and manufacturing
Knowledge in 2.5D/3D, flipchip, WLP and wirebond assembly and reliability
Knowledge in SPICE, signal/power integrity, DDR3/4, and SerDes channel modeling for high speed design

Education Requirements

Bachelors with 4+ years or Masters in EE or related fields

Years of Experience
A minimum of 2 years of relevant experience in advanced package design

  Contact Information
Reference Name (If Any): 





 
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