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Xilinx India Technology Services Pvt Ltd
  Company Profile
Xilinx leads the Programmable Logic Device (PLD) market - one of the fastest growing segments of the semiconductor industry. Founded in 1984 and headquartered in San Jose, California, we are a $1.9 billion company with an employee base of over 3300 professionals across our global offices. We take pride in nurturing innovation and providing our employees with a values-driven and rewarding workplace.
  Job Details 

Staff Design Engineer

Posted On:  1/13/2021 5:15:47 AM

Staff Design Engineer

No. of vacancies:  2
Qualifications:  Bachelor Degree
Essential Skills: 
Not specified
Minimum Total Experience:  1 Yrs
Job Tenure:  Contract - W2
Salary Offered:  Market Rate
Job Location:  Hyderabad Telangana India

  Job Description
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.

We are looking for a talented, self-driven and motivated engineer to be part of the Xilinx. In this position you will play a key role in the verification and validation of complex and next generation IPs and Systems for the future generations of the Xilinx tools and devices. Responsibilities would include understanding of system requirements, coming up with verification plans, writing system verilog testbenches and assertions, functional verification, integration with tool flow, hardware validation and also work with Xilinx quality assurance infrastructures to ensure a good quality IP/Sub-System delivery. The key skill requirements are as below:

B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 9+ years of relevant experience in IP verification and validation
Ability to lead RTL verification tasks for complex FPGA/complex design blocks by fully understanding the architecture and design specification
Interact with architects and design engineers to create a comprehensive verification test plan
Understanding of AMBA protocols like AXI4, AXI-STREAM and AHB is needed. Knowledge on high speed serial transceiver GT and interface

Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc
Proven end to end verification of complex IP using System Verilog and latest methodologies which include UVM, OVM, VMM
Proficient knowledge of System Verilog, HVL based methodology (UVM or OVM) and hands on scripting experience for automations

Experience in verification including constrained-random, coverage driven verification environments
Strong debugging, verification and board validation skills
Should have handled verification of complex RTL designs and validating them on the boards
Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
Having System level knowledge / Verifying IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus

Self-driven, motivated, result oriented individual with superior academic achievements
Excellent interpersonal, written, group communication and problem solving skills
Good organizational and execution skills with ability to multi-task and prioritize

  Contact Information
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