Description

Design and architect high-performance blocks for advanced networking ASICs, owning micro-architecture, logic design, and timing closure.

This role is on-site.

Responsibilities

• Architect high-performance blocks for advanced networking ASICs.
• Perform micro-architecture and logic design to optimize throughput and power consumption.
• Collaborate with verification teams on testplan development and debugging test failures.
• Work with physical design teams to develop timing constraints, analyze violations, and implement timing fixes.

Required Skills

• 5+ years of ASIC design experience.
• Strong Verilog RTL coding skills.
• MSEE or BSEE degree.
• Knowledge of high-performance memory subsystems.
• Knowledge of multi-domain clock synchronization and high-speed serial interfaces.
• Strong ASIC debugging and problem-solving skills.
• Experience with Synopsys Design Compiler, Verplex LEC, and Spyglass.

Preferred Skills

• Experience designing ASICs for networking protocols such as Ethernet or FCoE.

Key Skills

Education

Any graduate