41 synopsys design compiler Jobs | iitjobs

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ASIC Design Engineer Juniper Networks

• 1+ year of experience

•

N/A

•

1 opening

Synopsys Design Compiler Verplex LEC ASIC design

Bangalore, Karnataka, India

Senior Engineer - Memory Design Validation HRP Global Technologies

• 7+ year of experience

•

N/A

•

1 opening

Spcie (hspice & Pspice)Spectre Calibre Synopsys’ Nanosim Cadence’s Ultrasim

Bloomington, MN, USA

ASIC Design Engineer Blue Origin IT Staffing

• 10+ year of experience

•

N/A

•

1 opening

San Jose, CA, USA

SOC Design Verification Engineer Ztek Consulting Inc

• 10+ year of experience

•

N/A

•

1 opening

Git Shell Perl Python Integration

Santa Clara, CA, USA

ASIC Emulation Engineer Canvendor

• 5+ year of experience

•

N/A

•

1 opening

SystemVerilog Verilog RTL Design Synopsys Cadence

San Francisco Bay Area, CA, USA

FPGA Logic Design Engineer Intime Infotech Inc

• 7+ year of experience

•

N/A

•

1 opening

Python Tcl Perl Vhdl C

North Reading, Massachusetts, USA

Senior Embedded Software Engineering Manager CareerNet Technologies Pvt Ltd

• 5+ year of experience

•

N/A

•

1 opening

Power Integrity Synopsys Eda Cadence Cadence Allegro

Bengaluru, Karnataka, India

DFX Verification Engineer ACL Digital

• 3+ year of experience

•

N/A

•

1 opening

Verilog Systemverilog Perl Python Tcl Scripts

Bengaluru, Karnataka, India

DFT Design Engineer Qcentrio

• 6+ year of experience

•

N/A

•

1 opening

ATPG SCAN MBIST JTAG Tessent

Bangalore, Karnataka, India

Micro Architect Zealogics

• 1+ year of experience

•

N/A

•

1 opening

C/C++Python scripting languages design automation microarchitecture design

Kochi, Kerala, India

Senior Software Engineer Redolent Inc

• 10+ year of experience

•

N/A

•

1 opening

Sunnyvale, CA, USA

Physical Design (STA) Engineer Haavia Inc

• 10+ year of experience

•

N/A

•

1 opening

PHYSICAL DESIGN ENGINEER SOC ARCHITECTURE DDR2 SDR LPDDR

Austin, TX, USA

Senior Analog Design and Layout Engineer KK Technologies LLC

• 5+ year of experience

•

N/A

•

1 opening

Layout Engineer Analog Design

Colorado Springs, CO, USA

FPGA Verification Engineer Saransh Inc

• 5+ year of experience

•

N/A

•

1 opening

Fpga Design Principles System Verilog Uvm Python Perl

Mountain View, CA, USA

UVM Development Engineer Avance Consulting

• 10+ year of experience

•

N/A

•

1 opening

Verification Simulation ABV Debugging UVM

Madrid,Spain