Description

You will design and implement digital intellectual property blocks for SoC environments.

This role is on-site.

Responsibilities

• Define micro-architecture and convert functional specifications into clean, synthesizable, and scalable RTL using Verilog/SystemVerilog.
• Integrate digital IP blocks into top-level SoC environments and support bus interfaces including AHB, APB, and AXI.
• Resolve synthesis warnings, lint violations, CDC issues, and static timing analysis (STA) comments.
• Collaborate with Design Verification teams for debug and validation.

Required Skills

• 5+ years of experience in RTL design and digital IP development.
• Strong proficiency in Verilog and SystemVerilog-based RTL design and synthesis flows.
• Hands-on experience with linting tools, including Spyglass, and CDC/RDC analysis.
• Proven experience with SoC integration and standard bus protocols (AXI/AHB/APB).
• Familiarity with STA concepts, timing closure, and synthesis tools.
• Understanding of low-power design methodologies.

Key Skills

Education

Any Graduate