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HRP Global Technologies Logo
RTL Design Engineer (IP Level)HRP Global Technologies

• 4-12 year of experience

•

N/A

•

1 opening

Synopsys Design CompilerSpyglassSpyglass CdcCadence GenusJaspergold

Bangalore, Karnataka, India

CareerNet Technologies Pvt Ltd Logo
Design Engineer (IP Design)CareerNet Technologies Pvt Ltd

• 5+ year of experience

•

N/A

•

1 opening

LintRtl DesignCdcSpyglassVerilog

Bengaluru, Karnataka, India

Ztek Consulting Inc Logo
Sr. Logic Design (RTL) EngineerZtek Consulting Inc

• 12+ year of experience

•

N/A

•

1 opening

PerlPythonTclLogic (rtl) Design

Santa Clara, CA, USA (remote)

Juniper Networks Logo
ASIC Design EngineerJuniper Networks

• 1+ year of experience

•

N/A

•

1 opening

Synopsys Design CompilerVerplex LECASIC design

Bangalore, Karnataka, India

ACL Digital Logo
Senior RTL Design EngineerACL Digital

• 5+ year of experience

•

N/A

•

1 opening

Application-Specific Integrated Circuits (ASIC)C (Programming Language)Hardware ArchitectureMicroarchitecturePerl

Bengaluru, Karnataka, India

Ampcus Logo
Principal Verification EngineerAmpcus

• 1+ year of experience

•

N/A

•

1 opening

SOC

San Francisco, CA, USA

Redolent Inc Logo
Design Verification EngineerRedolent Inc

• 7+ year of experience

•

N/A

•

1 opening

C-shell ScriptingVerilog-hdlSystem VerilogPythonC

Santa Clara, CA, USA

Techgene Logo
Principal Verification EngineerTechgene

• 7+ year of experience

•

N/A

•

1 opening

GPIOUARTSPISWJTAG

San Francisco, CA, USA

Intime Infotech Inc Logo
FPGA Logic Design EngineerIntime Infotech Inc

• 7+ year of experience

•

N/A

•

1 opening

PythonTclPerlVhdlC

North Reading, Massachusetts, USA