Description

You will design and implement RTL code for IP blocks at the IP and SoC integration levels.

This role is on-site.

Responsibilities

• Develop and implement RTL code for IP blocks using Verilog and SystemVerilog.
• Perform synthesis using Synopsys Design Compiler or Cadence Genus.
• Execute linting and CDC analysis using SpyGlass or JasperGold.
• Apply low-power design techniques to IP implementations.
• Debug complex design issues and optimize RTL performance.

Required Skills

• 4 to 12 years of experience in RTL design.
• Proficiency in Verilog and SystemVerilog.
• Hands-on experience with Synopsys Design Compiler or Cadence Genus.
• Experience with linting and CDC tools such as SpyGlass or SpyGlass CDC.
• Working knowledge of JasperGold or similar formal verification tools.
• Competency in scripting with Python or Tcl.
• Understanding of PCIe protocol and implementation.
• Experience with Design IPs including PCIe Gen5, I2C, UCI, and HBM.
• Knowledge of AMBA protocols including APB, AHB, and AXI.

Preferred Skills

• Experience with SoC Integration.

Key Skills

Education

Any Graduate