8904 certification engineer Jobs | iitjobs

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Showing 46 - 60 of 8904 jobs

Design Verification Engineer SAI Technologies

• 5+ year of experience

•

No Preference/Any

•

2 opening

Rtl Synthesis Systemverilog Uvm Python

Austin, TX, USA

30+ days ago

FPGA Verification Engineer Agile IT Service

• 10+ year of experience

•

No Preference/Any

•

1 opening

Systemverilog Uvm Synopsys Python Perl

Mountain View, CA, USA

30+ days ago

Design Verification Engineer HRP Global Technologies

• 4-12 year of experience

•

Full-time Only

•

2 opening

Systemverilog (sv)Uvm Vhdl

Pune, Maharashtra, India

30+ days ago

SoC Verification Engineer Provance Business Consulting

• 6+ year of experience

•

No Preference/Any

•

1 opening

Systemverilog Uvm Debugging Testbench Architecture

Bangalore, Karnataka, India

30+ days ago

Design Verification Engineer Canvendor

• 5+ year of experience

•

No Preference/Any

•

1 opening

AMBA ARM Architecture SoC UVM

Dallas, TX, USA

30+ days ago

Principal Verification Engineer Techgene

• 7+ year of experience

•

Contract - Corp-to-Corp

•

1 opening

GPIO UART SPI SW JTAG

San Francisco, CA, USA

30+ days ago

SOC Verification Engineer Pure Storage

• 5+ year of experience

•

No Preference/Any

•

1 opening

SOC Verification Verilog UVM SV

Bangalore, Karnataka, India

30+ days ago

FPGA Verification Engineer Torque Technologies

• 5+ year of experience

•

No Preference/Any

•

2 opening

Fpga Uvm System Verlilog

Santa Clara, CA, USA

30+ days ago

FPGA Verification Engineer Kaizen Soft Solutions

• 5+ year of experience

•

Contract - Corp-to-Corp

•

1 opening

Fpga Uvm Python Perl Fpga Verification

Santa Clara, CA, USA

30+ days ago

Design Verification Engineer E-Solutions

• 5+ year of experience

•

No Preference/Any

•

2 opening

Confluence Jira Git

San Jose, California, USA

30+ days ago

Staff Verification Engineer Talent21

• 6+ year of experience

•

No Preference/Any

•

2 opening

written verbal communication Problem Solving Arm Logic Verification Debug Infrastructure

Bengaluru, Karnataka, India

30+ days ago

Design Verification Engineer Virtuxinet Technologies

• 5+ year of experience

•

Contract - W2

•

1 opening

Perl Python Gls

United States (remote)

30+ days ago

Design Verification Engineer Niksperri

• 4+ year of experience

•

No Preference/Any

•

1 opening

C/c++System Verilog verification Scripting Language Shell Makefile

Bengaluru, Karnataka, India

30+ days ago

Software Verification Engineer VDart

• 5+ year of experience

•

Contract - Corp-to-Corp

•

1 opening

Python Java test automation FDA 21 CFR Part 820 ISO 13485

Palo Alto, CA, USA

30+ days ago

Senior Design Verification Engineer Lancesoft

• 6+ year of experience

•

No Preference/Any

•

2 opening

AXI C (Programming Language)C++Computer Engineering Functional Verification

Markham, ON, Canada

30+ days ago

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