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Showing 61 - 75 of 77 jobs

Physical Design Engineer Ztek Consulting Inc

• 10+ year of experience

•

Contract - Corp-to-Corp

•

1 opening

Perl Python Unix System Tcl/tk

San Jose, CA, USA

30+ days ago

RTL Design Engineer (IP Level)HRP Global Technologies

• 4-12 year of experience

•

No Preference/Any

•

1 opening

Synopsys Design Compiler Spyglass Spyglass Cdc Cadence Genus Jaspergold

Bangalore, Karnataka, India

30+ days ago

Senior Embedded Software Engineering Manager CareerNet Technologies Pvt Ltd

• 10+ year of experience

•

No Preference/Any

•

1 opening

Power Integrity Synopsys Eda Cadence Cadence Allegro

Bengaluru, Karnataka, India

30+ days ago

DFT Lead ACL Digital

• 10+ year of experience

•

No Preference/Any

•

1 opening

Automatic Test Pattern Generation (ATPG)Boundary Scan Computer Simulations DFT Debugging

Bengaluru, Karnataka, India

30+ days ago

Senior Software Engineer Redolent Inc

• 10+ year of experience

•

Contract - Corp-to-Corp

•

1 opening

Sunnyvale, CA, USA

30+ days ago

SoC Pre-Silicon Verification Engineer Zealogics

• 1+ year of experience

•

No Preference/Any

•

1 opening

SystemVerilog C/C++Perl or Python

Kochi, Kerala, India

30+ days ago

Physical Design Engineer UST

• 4+ year of experience

•

No Preference/Any

•

1 opening

Tcl Perl Shell Python Apache

Penang, Malaysia

30+ days ago

Design Verification Engineer HRP Global Technologies

• 4-12 year of experience

•

Full-time Only

•

2 opening

Systemverilog (sv)Uvm Vhdl

Pune, Maharashtra, India

30+ days ago

Lead IP Verification Engineer CareerNet Technologies Pvt Ltd

• 8+ year of experience

•

No Preference/Any

•

1 opening

System Verilog Uvm Verification Digital Design Systemverilog Assertions

Hyderabad, Telangana, India

30+ days ago

Senior AI Infrastructure Engineer ACL Digital

• 5+ year of experience

•

Full-time Only

•

1 opening

Python Shell Scripting Jenkins Linux Llm

Austin, TX, USA

30+ days ago

Physical Design Engineer Zealogics

• 1+ year of experience

•

No Preference/Any

•

1 opening

Tcl Perl or Python CAD

Kerala, India

30+ days ago

STA Engineer HRP Global Technologies

• 4-12 year of experience

•

No Preference/Any

•

1 opening

Synopsys Primetime Cadence Tempus Scripting (tcl Perl)Verilog

Bangalore, Karnataka, India

30+ days ago

Senior Embedded Software Engineering Manager CareerNet Technologies Pvt Ltd

• 5+ year of experience

•

No Preference/Any

•

1 opening

Power Integrity Synopsys Eda Cadence Cadence Allegro

Bengaluru, Karnataka, India

30+ days ago

DFX Verification Engineer ACL Digital

• 3+ year of experience

•

Full-time Only

•

1 opening

Verilog Systemverilog Perl Python Tcl Scripts

Bengaluru, Karnataka, India

30+ days ago

IP/SS Pre-Silicon Verification Lead Zealogics

• 1+ year of experience

•

No Preference/Any

•

1 opening

SystemVerilog C/C++Perl Python

Kochi, Kerala, India

30+ days ago

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