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Showing 31 - 45 of 3669 jobs

SoC Verification Engineer Provance Business Consulting

• 6+ year of experience

•

No Preference/Any

•

1 opening

Systemverilog Uvm Debugging Testbench Architecture

Bangalore, Karnataka, India

30+ days ago

Design Verification Engineer Canvendor

• 5+ year of experience

•

No Preference/Any

•

1 opening

C++OOP System Verilog UVM OVM

San Jose, CA, USA

30+ days ago

Design Verification Engineer Niksperri

• 4+ year of experience

•

No Preference/Any

•

1 opening

C/c++System Verilog verification Scripting Language Shell Makefile

Bengaluru, Karnataka, India

30+ days ago

Senior Verification Engineer 4A IT Services LLC

• 5+ year of experience

•

No Preference/Any

•

1 opening

System Verilog C/c++Python

Bengaluru, Karnataka, India

30+ days ago

Design Verification Engineer E-Solutions

• 5+ year of experience

•

No Preference/Any

•

2 opening

Confluence Jira Git

San Jose, California, USA

30+ days ago

Design Verification Engineer PROLIM Infosystems

• 5+ year of experience

•

No Preference/Any

•

1 opening

System Verilog C++Uvm Axi Amba

Austin, TX, USA

30+ days ago

Validation & Verification Engineer Stellent IT LLC

• 5+ year of experience

•

Contract - Corp-to-Corp

•

1 opening

SDLC CSV Jira Waterfall MS SQL

Hayward, CA, USA

30+ days ago

Design Verification Lead Tanisha Systems Inc

• 10+ year of experience

•

No Preference/Any

•

1 opening

Application-Specific Integrated Circuits (ASIC)Computer Simulations System on a Chip (SoC)SystemVerilog Unified Power Format (UPF)

San Jose, CA, USA

30+ days ago

Design Verification Engineer with Python Coding Largeton

• 5+ year of experience

•

Full-time Only

•

1 opening

Python Uvm Api Testing

Sunnyvale, CA, USA (remote)

30+ days ago

Design Verification Engineer DBSI Services

• 5+ year of experience

•

No Preference/Any

•

2 opening

C C++Perl Python Tcl

Milpitas, CA, USA

30+ days ago

Design Verification Engineer Platinum Infosys Inc

• 8+ year of experience

•

No Preference/Any

•

1 opening

Pnr Jira Perl Python

USA (remote)

30+ days ago

Design Verification Engineer Intelliswift Software

• 7+ year of experience

•

No Preference/Any

•

1 opening

C/c++Python Tcl Perl Shell

Austin, TX, USA

30+ days ago

Design Verification Engineer XpertTech,Inc

• 3+ year of experience

•

Contract - Corp-to-Corp, Contract - Independent, Contract - W2

•

1 opening

Facebook is the End Client UVM/ System Verilog - sequences driver monitor scoreboard agent development System Verilog OVM/UVM Python Perl Shell scripting assertions (SVA) Digital ASICs Design

Boston, MA, USA (remote)

30+ days ago

Senior Design Verification Engineer Lancesoft

• 6+ year of experience

•

No Preference/Any

•

2 opening

AXI C (Programming Language)C++Computer Engineering Functional Verification

Markham, ON, Canada

30+ days ago

Design Verification Engineer Precision Technologies

• 5+ year of experience

•

Full-time Only

•

1 opening

Verilog System Verilog C/c++

Austin, TX, USA

30+ days ago

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